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? semiconductor components industries, llc, 2015 april, 2015 ? rev. 2 1 publication order number: kaf?0402/d kaf-0402 768 (h) x 512 (v) full frame ccd image sensor description the kaf?0402 image sensor is a high performance area ccd (charge-coupled device) image sensor with 768 (h) 512 (v) photoactive pixels designed for a wide range of image sensing applications. the sensor incorporates true two-phase ccd technology, simplifying the support circuits required to drive the sensor as well as reducing dark current without compromising charge capacity. the sensor also utilizes the truesense transparent gate electrode to improve sensitivity compared to the use of a standard front side illuminated polysilicon electrode. optional microlenses focus the majority of the light through the transparent gate, increasing the optical response further. table 1. general specifications parameter typical value architecture full frame ccd, enhanced response total number of pixels 784 (h) 520 (v) number of active pixels 768 (h) 512 (v) = approx. 0.4 mp pixel size 9.0 m (h) 9.0 m (v) active image size 6.91 mm (h) 4.6 mm (v) 8.3 mm (diagonal) 1/2 optical format die size 8.4 mm (h) 5.5 mm (v) aspect ratio 3:2 saturation signal 100,000 electrons quantum efficiency (with microlens) peak: 77% 400 nm: 45% quantum efficiency (no microlens) peak: 65% 400 nm: 30% output sensitivity 10 v/e ? read noise 15 electrons dark current < 10 pa/cm 2 at 25 c dark current doubling temperature 6.3 c dynamic range 76 db charge transfer efficiency > 0.99999 blooming suppression none maximum date rate 10 mhz package cerdip package (sidebrazed) cover glass clear or ar coated, 2 sides note: parameters above are specified at t = 25 c unless otherwise noted. www.onsemi.com figure 1. kaf?0402 full frame ccd image sensor applications ? digitization ? medical ? scientific see detailed ordering and shipping information on page 2 o f this data sheet. ordering information
kaf?0402 www.onsemi.com 2 ordering information table 2. ordering information ? kaf?0402 image sensor part number description marking code kaf?0402?aaa?cb?b1 monochrome, no microlens, cerdip package (sidebrazed), clear cover glass (no coatings), grade 1 kaf?0402?aaa serial number kaf?0402?aaa?cb?ae monochrome, no microlens, cerdip package (sidebrazed), clear cover glass (no coatings), engineering sample kaf?0402?aaa?cp?b1 monochrome, no microlens, cerdip package (sidebrazed), taped clear cover glass (no coatings), grade 1 kaf?0402?aaa?cp?b2 monochrome, no microlens, cerdip package (sidebrazed), taped clear cover glass (no coatings), grade 2 kaf?0402?aaa?cp?ae monochrome, no microlens, cerdip package (sidebrazed), taped clear cover glass (no coatings), engineering sample kaf?0402?aba?cd?b1 monochrome, telecentric microlens, cerdip package (sidebrazed), clear cover glass with ar coating (both sides), grade 1 kaf?0402?aba serial number kaf?0402?aba?cd?b2 monochrome, telecentric microlens, cerdip package (sidebrazed), clear cover glass with ar coating (both sides), grade 2 kaf?0402?aba?cd?ae monochrome, telecentric microlens, cerdip package (sidebrazed), clear cover glass with ar coating (both sides), engineering sample kaf?0402?aba?cp?b1 monochrome, telecentric microlens, cerdip package (sidebrazed), taped clear cover glass (no coatings), grade 1 kaf?0402?aba?cp?b2 monochrome, telecentric microlens, cerdip package (sidebrazed), taped clear cover glass (no coatings), grade 2 kaf?0402?aba?cp?ae monochrome, telecentric microlens, cerdip package (sidebrazed), taped clear cover glass (no coatings), engineering sample table 3. ordering information ? evaluation support part number description kaf?0402?12?5?a?evk evaluation board (complete kit) see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com .
kaf?0402 www.onsemi.com 3 device description architecture figure 2. block diagram 768 active pixels/line v rd r v dd v out v ss sub v og 4 dark 10 inactive 12 dark 2 inactive 4 dark lines v1 v2 guard h1 h2 kaf?0402 usable active image area 768 (h) 512 (v) 9 9 m pixels 3:2 aspect ratio 4 dark lines the sensor consists of 784 parallel (vertical) ccd shift registers each 520 elements long. these registers act as both the photosensitive elements and as the transport circuits that allow the image to be sequentially read out of the sensor. the parallel (vertical) ccd registers transfer the image one line at a time into a single 796-element (horizontal) ccd shift register. the horizontal register transfers the charge to a single output amplifier. the output amplifier is a two-stage source follower that converts the photo-generated charge to a voltage for each pixel. microlenses microlenses are formed along each row. they are effectively half of a cylinder centered on the transparent gates, extending continuously in the row direction. they act to direct the photons away from the polysilicon gate and through the transparent gate. this increases the response, especially at the shorter wavelengths (< 600 nm). figure 3. microlens silicon microlens v1 v2
kaf?0402 www.onsemi.com 4 figure 4. output schematic source follower #1 source follower #2 hccd charge transfer floating diffusion v dd v out v rd v og r h2 h2 h1 h1 output structure charge presented to the floating diffusion is converted into a voltage and current amplified in order to drive of f-chip loads. the resulting voltage change seen at the output is linearly related to the amount of charge placed on the floating dif fusion. once the signal has been sampled by the system electronics, the reset gate ( r) is clocked to remove the signal and the floating diffusion is reset to the potential applied by vrd (see figure 4). more signal at the floating diffusion reduces the voltage seen at the output pin. in order to activate the output structure, an off-chip load must be added to the vout pin of the device such as shown in figure 8. dark reference pixels there are 4 light shielded pixels at the beginning of each line, and 12 at the end. there are 4 dark lines at the start of every frame and 4 dark lines at the end of each frame. under normal circumstances, these pixels do not respond to light. however, dark reference pixels in close proximity to an active pixel can scavenge signal depending on light intensity and wavelength and therefore will not represent the true dark signal. dummy pixels within the horizontal shift register are 10 leading additional pixels that are not associated with a column of pixels within the vertical register. these pixels contain only horizontal shift register dark current signal and do not respond to light. a few leading dummy pixels may scavenge false signal depending on operating conditions. there are two more dummy pixels at the end of each line. image acquisition an electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs within the sensor. these photon induced electrons are collected locally by the formation of potential wells at each photogate or pixel site. the number of electrons collected is linearly dependent on light level and exposure time and non-linearly dependent on wavelength. when the pixel?s capacity is reached, excess electrons will leak into the adjacent pixels within the same column. this is termed blooming. during the integration period, the v1 and v2 register clocks are held at a constant (low) level. see figure 9. charge transport referring again to figure 10, the integrated charge from each photogate is transported to the output using a two-step process. each line (row) of charge is first transported from the vertical ccd to the horizontal ccd register using the v1 and v2 register clocks. the horizontal ccd is presented a new line on the falling edge of v2 while h1 is held high. the horizontal ccd then transports each line, pixel by pixel, to the output structure by alternately clocking the h1 and h2 pins in a complementary fashion. on each falling edge of h2 a new charge packet is transferred onto a floating diffusion and sensed by the output amplifier.
kaf?0402 www.onsemi.com 5 physical description pin description and device orientation figure 5. pinout diagram vog 1 vout 2 vdd 3 vrd 4 r5 vss 6 h1 7 h2 8 n/c 9 n/c 10 vsub 11 n/c 12 pin 1 pixel 1,1 13 n/c 14 vsub 15 v1 16 v1 17 v2 18 v2 19 v2 20 v2 21 v1 22 v1 23 guard 24 n/c table 4. pin description pin name description 1 vog output gate 2 vout video output 3 vdd amplifier supply 4 vrd reset drain 5 r reset clock 6 vss amplifier supply return 7 h1 horizontal ccd clock ? phase 1 8 h2 horizontal ccd clock ? phase 2 9 n/c no connection 10 n/c no connection 11 vsub substrate 12 n/c no connection pin name description 13 n/c no connection 14 vsub substrate 15 v1 vertical ccd clock ? phase 1 16 v1 vertical ccd clock ? phase 1 17 v2 vertical ccd clock ? phase 2 18 v2 vertical ccd clock ? phase 2 19 v2 vertical ccd clock ? phase 2 20 v2 vertical ccd clock ? phase 2 21 v1 vertical ccd clock ? phase 1 22 v1 vertical ccd clock ? phase 1 23 guard guard ring 24 n/c no connection
kaf?0402 www.onsemi.com 6 imaging performance specifications electro-optical all values measured at 25 c and nominal operating conditions. these parameters exclude defective pixels. table 5. specifications description symbol min. nom. max. units notes verification plan saturation signal vertical ccd capacity horizontal ccd capacity output node capacity n sat 85,000 170,000 190,000 100,000 200,000 220,000 ? 240,000 ? e ? /pix 1 design 9 quantum efficiency (see figure 6) ? ? ? design 9 photoresponse non-linearity prnl ? 1.0 2.0 % 2 photoresponse non-uniformity prnu ? 0.8 ? % 3 die 8 dark signal j dark ? ? 15 6 30 10 e ? /pix/sec pa/cm 2 4 die 8 dark signal doubling temperature ? 6.3 7 c design 9 dark signal non-uniformity dsnu ? 15 30 e ? /pix/sec 5 die 8 dynamic range dr 72 76 ? db 6 design 9 charge transfer efficiency cte 0.99997 0.99999 ? die 8 output amplifier dc offset v odc v rd v rd + 0.5 v rd + 1.0 v design 9 output amplifier sensitivity v out /n e ? 9 10 ? v/e ? design 9 output amplifier output impedance z out 180 200 220 design 9 noise floor n e ? ? 15 20 electrons 7 1. for pixel binning applications, electron capacity up to 330,000 can be achieved with modified ccd inputs. 2. worst case deviation from straight line fit, between 2% and 90% of v sat . 3. one sigma deviation of a 128 128 sample when ccd illuminated uniformly at half of saturation. 4. average of all pixels with no illumination at 25 c. 5. average dark signal of any of 11 8 blocks within the sensor (each block is 128 128 pixels). 6. 20log (n sat /n e ? ) at nominal operating frequency and 25 c. 7. noise floor is specified at the nominal pixel frequency and excludes any dark or pattern noises. it is dominated by the output amplif ier power spectrum with a bandwidth = 5 ? pixel rate. 8. a parameter that is measured on every sensor during production testing. 9. a parameter that is quantified during the design verification activity.
kaf?0402 www.onsemi.com 7 typical performance curves figure 6. typical spectral response 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 400 500 600 700 800 900 1000 absolute quantum efficiency kaf?0402 spectral response kaf?0402 (with microlenses) kaf?0402 (no microlenses) wavelength (nm)
kaf?0402 www.onsemi.com 8 defect definitions table 6. specifications (defect tests performed at t = 25 c) grade point defect cluster defect column defect c1 < 5 0 0 c2 < 10 < 4 0 point defects dark: a pixel which deviates by more than 6% from neighboring pixels when illuminated to 70% of saturation. bright: a pixel whose dark current > 5,000 e ? /pix/sec at 25 c. cluster defect a grouping of not more than 5 adjacent point defects. column defect a grouping of > 5 contiguous point defects along a single column. a column containing a pixel with dark current > 12,000 e ? /pix/sec at 25 c (bright column). a column that does not meet the minimum vertical ccd charge capacity (low charge capacity column). a column that loses > 250 e ? under 2 ke ? (trap defect). neighboring pixels the surrounding 128 128 pixels or 64 columns/rows. defect separation column and cluster defects are separated by no less than 2 pixels in any direction (excluding single pixel defects). figure 7. active pixel region 1, 512 1, 1 768, 512 768, 1
kaf?0402 www.onsemi.com 9 operation table 7. absolute maximum ratings description symbol minimum maximum units notes diode pin voltages v diode 0 20 v 1, 2 gate pin voltages v gate1 ?16 16 v 1, 3, 5 output bias current i out ? ?10 ma 4 output load capacitance c load ? 15 pf 4 stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. referenced to pin vsub or between each pin in this group. 2. includes pins: vrd, vdd, vss, vout. 3. includes pins: v1, v2, h1, h2, vog, vlg, r. 4. avoid shorting output pins to ground or any low impedance source during operation. 5. this sensor contains gate protection circuits to provide some protection against esd events. the circuits will turn on when greater than 16 v appears between any two gate pins. permanent damage can result if excessive current is allowed to flow under these conditions. table 8. dc bias operating conditions description symbol minimum nominal maximum units maximum dc current (ma) notes reset drain v rd 10 11.0 11.5 v 0.01 output amplifier return v ss 1.5 2.0 2.5 v ?0.5 output amplifier supply v dd 14.75 15 15.5 v i out substrate v sub 0 0 0 v 0.01 output gate v og 3.75 4 5 v 0.01 guard ring guard 8.0 9.0 12.0 v 0.01 video output current i out ? ?5 ?10 ma ? 1 1. an output load sink must be applied to v out to activate output amplifier ? see figure 8. figure 8. example output structure load diagram buffered output 2n3904 or equivalent 0.1 f 1 k 140 v out +15 v ~5ma
kaf?0402 www.onsemi.com 10 ac operating conditions table 9. clock levels description symbol level minimum nominal maximum units effective capacitance vertical ccd clock ? phase 1 v1 low ?10.5 ?10 ?9.5 v 6 nf (all v1 pins) vertical ccd clock ? phase 1 v1 high ?0.5 0 1.0 v 6 nf (all v1 pins) vertical ccd clock ? phase 2 v2 low ?10.5 ?10.0 ?9.5 v 6 nf (all v2 pins) vertical ccd clock ? phase 2 v2 high ?0.5 0 1.0 v 6 nf (all v2 pins) horizontal ccd clock ? phase 1 h1 low ?4.5 ?4.0 ?3.5 v 50 pf horizontal ccd clock ? phase 1 h1 amplitude 9.5 10.0 10.5 v 50 pf horizontal ccd clock ? phase 2 h2 low ?4.5 ?4.0 ?3.5 v 50 pf horizontal ccd clock ? phase 2 h2 amplitude 9.5 10.0 10.5 v 50 pf reset clock r low ?3.0 ?2.0 ?1.75 v 5 pf reset clock r amplitude 5.0 6.0 7.0 v 5 pf 1. all pins draw less than 10 a dc current. 2. capacitance values relative to v sub .
kaf?0402 www.onsemi.com 11 timing table 10. requirements and characteristics description symbol minimum nominal maximum units notes h1, h2 clock frequency f h ? 4 10 mhz 1, 2, 3 pixel period (1 count) t pix 100 250 ? ns h1, h2 set-up time t hs 0.5 1 ? s v1, v2 clock pulse width t v 1.5 2 ? s 2 reset clock pulse width t r 10 20 ? ns 4 readout time t readout 43.7 107 ? ms 5 integration time t int ? ? ? 6 line time t line 84.1 206 ? s 7 1. 50% duty cycle values. 2. cte may degrade above the nominal frequency. 3. rise and fall times (10/90% levels) should be limited to 5?10% of clock period. crossover of register clocks should be betwee n 40?60% of amplitude. 4. r should be clocked continuously. 5. t readout = (520 ? t line ) 6. integration time (t int ) is user specified. longer integration times will degrade noise performance due to dark signal fixed pattern and shot noise. 7. t line = (3 ? t v ) + t hs + (796 ? t pix ) + t pix frame timing figure 9. frame timing diagram frame timing t readout t int 1 frame = 520 lines 520 519 2 1 line v1 v2 h1 h2
kaf?0402 www.onsemi.com 12 line timing and pixel timing figure 10. line and pixel timing diagrams photoactive line timing detail pixel timing detail line content dark reference dummy pixels 1?10 11?14 15?782 783?794 795?796 v sat saturated pixel video output signal v dark video output signal in no-light situation, not zero due to j dark v pix pixel video output signal level, more electrons = more negative v odc video level offset with respect to v sub * v sub analog ground * see image acquisition section. v1 v2 h1 h2 r 1 line = 796 pixels t v t hs t pix 796 counts t v h1 h2 r v out t r t pix v sat v dark v odc v sub v pix 1 count
kaf?0402 www.onsemi.com 13 storage and handling table 11. storage conditions description symbol minimum maximum units notes storage temperature t st ? 100 c humidity rh 5 90 % 1 1. t = 25 c. excessive humidity will degrade mttf. for information on esd and cover glass care and cleanliness, please download the image sensor handling and best practices application note (an52561/d) from www.onsemi.com . for information on soldering recommendations, please download the soldering and mounting techniques reference manual (solderrm/d) from www.onsemi.com . for quality and reliability information, please download the quality & reliability handbook (hbd851/d) from www.onsemi.com . for information on device numbering and ordering codes, please download the device nomenclature technical note (tnd310/d) from www.onsemi.com . for information on standard terms and conditions of sale, please download terms and conditions from www.onsemi.com .
kaf?0402 www.onsemi.com 14 mechanical information completed assembly figure 11. completed assembly (1 of 2)
kaf?0402 www.onsemi.com 15 figure 12. completed assembly (2 of 2)
kaf?0402 www.onsemi.com 16 on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 kaf?0402/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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